This invention pertains to electroless plating of conductive materials on work pieces (or “substrates”) such as partially fabricated integrated circuits. More particularly, the invention pertains to spin plating electroless deposition of very thin conductive layers (in the range of a few hundred angstroms).
Various unit processes are available for plating thin metallic layers such as seed layers (used as a conductive coating for electrodeposition of copper). These processes include chemical vapor deposition (CVD), electroplating, physical vapor deposition (PVD), and electroless plating. In many ways electroless plating is an attractive choice. It has a lower cost than electroplating. It has excellent step coverage (better than at least PVD). And it allows for selective deposition on regions of different chemical or structural composition on the substrate.
Because of these advantages, various groups are actively researching certain applications for electroless plating. These include repairing PVD (physical vapor deposition) seed layers, forming thin seed and barrier layers, and capping layers for copper lines. Regarding seed layer repair, seed layers are typically formed by PVD. But as device geometries shrink, the step coverage of PVD begins to fail to the point where copper incompletely covers the bottoms of the contact holes in Damascene structures. Electroless plating can repair the incomplete PVD seed layer by depositing copper on inadequately covered regions of Damascene structures.
In a second application, electroless plating provides a metallic barrier layer that serves a dual role as a seed layer. In one example, electroless plating deposits a layer of metallic cobalt that blocks diffusion of copper into surrounding dielectric and serves as a seed layer for the subsequent electrodeposition of copper.
Finally, electroless plating may form a “capping layer” that reduces or eliminates copper electromigration from an underlying metal layer to a diffusion barrier deposited on the dielectric layer of the next higher metallization layer. Electromigration is known to be a particular problem at the interface of a copper line in lower metallization layer and a porous diffusion barrier in the next higher metallization layer. A thin metal capping layer interposed between the diffusion barrier and copper line addresses this problem. Electroless plating of an appropriate metal layer such as a cobalt layer can provide effective capping.
While research in electroless plating for these applications is proceeding and new advances are occurring rapidly, certain difficulties remain. For example, it can be difficult to accurately control the thickness of the deposited layer, particularly when very thin layers are employed (on the order of tens or hundreds of angstroms). Further, metal layers formed by electroless deposition are frequently of poor quality. Electroless deposition is essentially a two step process: nucleation and bulk growth. Nucleation is the rate limiting step. To promote nucleation, conventional electroless processes employ plating solutions having very high reactant concentrations. While this addresses the issue of nucleation, it can introduce a different problem during the bulk growth phase. For once the growth phase begins it proceeds very rapidly due to the high reactant concentrations. The rapid deposition results in relatively high rates of defects such as dislocations. Further, it can cause impurities such as chloride ions and carbon to incorporate in the metal layer. These impurities originate with the anions, complexing agents, surfactants, etc. in the plating solution.
Thus, while electroless processes appear to be an attractive candidates for next generation IC fabrication processes, certain problems remain to be solved.